1. Field of the Invention
The present invention relates generally to dynamic semiconductor memory devices, and more particularly, to a semiconductor memory device in which a read error is reduced.
2. Description of the Prior Art
FIG. 1 is a diagram showing a structure of a main portion of a conventional dynamic random access memory (referred to as DRAM hereinafter).
In FIG. 1, a plurality of pairs of bit lines BL and BL are arranged intersecting with a plurality of word lines WL. Memory cells MC are connected to intersections of the bit lines BL or BL and the word lines WL, respectively. Each of the memory cells MC comprises a transfer gate TG formed of an N channel MOS transistor and a capacitance Cs storing information of an "H" or "L" level. In addition, dummy word lines DWL0 and DWL1 are arranged intersecting with the bit line pairs BL and BL. A dummy cell DC0 is provided at an intersection of the dummy word line DWL0 and each of the bit lines BL, and a dummy cell DC1 is provided at an intersection of the dummy word line DWL1 and each of the bit lines BL. An intermediate potential V.sub.CC /2 between a power-supply potential V.sub.CC and a ground potential is stored in the dummy cells DC0 and DC1.
Furthermore, a sense amplifier SA is connected between each of the bit line pairs BL and BL. The plurality of word lines WL and the dummy word lines DWL0 and DWL1 are connected to a row decoder 101. The bit line pairs BL and BL are connected to data input/output lines I/O and I/O through transfer gates Q1 and Q2 each formed of an N channel MOS transistor. The transfer gates Q1 and Q2 have their gates connected to a column decoder 102.
At the time of reading out data, a single word line WL is selected by the row recorder 101, so that a potential thereon is raised to the "H" level. Consequently, data stored in the memory cells MC connected to the word line WL are read out onto the corresponding bit lines BL or BL, respectively. For example, when data are read out onto the bit lines BL, a potential on the dummy word line DWL1 is raised to the "H" level, so that potentials in the dummy cells DC1 are read out onto the corresponding bit lines BL, respectively. Consequently, potentials on the bit lines BL become a reference potential. On the other hand, potentials on the bit lines BL are slightly higher or lower than the reference potential. Thereafter, the potential difference between each of the bit line pairs BL and BL is amplified by the corresponding sense amplifier SA. Either one pair of the transfer gates Q1 and Q2 is turned on by the column decoder 102, so that data on the bit line pair BL and BL connected thereto is read out onto the data input/output lines I/O and I/O.
Let's consider a potential which appears on each of the bit line pairs BL and BL at the time of reading out data.
As shown in FIG. 2, it is assumed that a capacitance C.sub.1 exists between each of the bit lines and the ground potential (fixed potential) through a cell plate or a substrate, a capacitance C.sub.2 exists between the paired bit lines, and a capacitance C.sub.3 exists between adjacent bit line pairs. In addition, it is assumed that a cell capacitance of the memory cell MC is represented by C.sub.S. Each of the bit lines is assumed to have a length l.
When data of the "H" level is stored in a memory cell by writing V.sub.CC, charges stored in the memory cell become C.sub.S V.sub.CC. On the other hand, when data of the "L" level is stored in the memory cell by writing OV, charges stored in the memory cell become zero. In addition, charges of C.sub.S V.sub.CC /2 (writing of V.sub.CC /2 or the like) are stored in the dummy cells DC0 and DC1, respectively. It is assumed that the bit line pair is precharged to a power-supply potential V.sub.CC before a reading operation.
Let's consider a case in which a memory cell connected to a bit line BL1 is selected and a dummy cell is connected to a bit line BL1. In this case, a potential V.sub.BL1 on the bit line BL1 and a potential V.sub.BL1 on the bit line BL1 become as follows: When the data of the "L" level is read out from the selected memory cell, the potential V.sub.BL1 on the bit line BL1 is represented by the following equation; ##EQU1## When the data of the "H" level is read out from the selected memory cell, the potential .DELTA.V.sub.BL1 on the bit line BL1 is represented by the following equation; ##EQU2## In addition, the potential V.sub.BL1 on the bit line BL1 is represented by the following equation; ##EQU3## where .DELTA.V.sub.BL0, .DELTA.V.sub.BL1, .DELTA.V.sub.BL1 and .DELTA.V.sub.BL2 indicate the changes in potentials on the bit lines represented by subscripts, respectively.
Considering that the precharge levels of the bit lines BL1 and BL1 are equal, the potential difference between the paired bit lines is represented by the following equation from calculation of the equations (1) to (3): ##EQU4## In the equation (4), "+" in a double sign ".+-." indicates the case of reading out data of the "H" level, and "-" in the double sign ".+-." indicates the case of reading out data of the "L" level. A first term of a right-hand side of the equation (4) indicates a substantial read voltage difference, and a second term thereof indicates noise components applied from a bit line BL0 in a bit line pair adjacent to the bit line pair BL1 and BL1 and a bit line BL2 in separate bit line pair adjacent thereto through a coupling capacitance.
Meanwhile, when a pitch between bit lines is decreased as integration density of the memory cell is increased, the capacitance C.sub.3 between the adjacent bit line pairs is increased, so that the second term of the equation (4) becomes larger. Consequently, a read voltage is damaged. As a result, a read margin is decreased and a soft error rate is deteriorated. As a result, a malfunction occurs.
In order to solve the above described problems, the inventors of the present invention have proposed a semiconductor memory device in which the decrease in amplitude of the read voltage due to noises which are caused between the adjacent bit line pairs by the capacitance between bit lines can be completely made zero.
In this semiconductor memory device, one or a plurality of intersecting portions are provided on bit line pairs, so that noises of capacitive coupling which the paired bit lines respectively receive from bit line pairs adjacent thereto are the same, whereby the read voltage difference is not decreased.
Referring now to FIG. 3, description is made on a structure of the proposed semiconductor memory device.
As shown in FIG. 3, each of the bit line pairs BL0 and BL0, BL1 and BL1, . . . is equally divided into areas a, b, c and d each having a length of l/4, respective bit lines in the bit line pairs intersecting with each other at equally divided points CP1, CP2 and CP3:
(1) The bit lines BL0 and BL0 intersect with each other at the equally divided point CP2. PA0 (2) The bit lines BL1 and BL1 intersect with each other at the equally divided points CP1 and CP3. PA0 (1)' The bit lines BL2 and BL2 intersect with each other at the equally divided point CP2. PA0 (2)' The bit lines BL3 and BL3 intersect with each other at the equally divided points CP1 and CP3.
More specifically, the bit lines in the bit line pairs in odd numbers counting from the bit line pair BL0 and BL0 intersect with each other at the equally divided point C2, while the bit lines in the bit line pairs in even numbers intersect with each other at the equally divided points CP1 and CP3. Consequently, noises of capacitive coupling which each of the bit lines receives from the adjacent bit lines are as follows, considered in the same manner as the conventional example shown in FIG. 2:
(1) Noises .DELTA.V.sub.BL1' and .DELTA.V.sub.BL1' which the bit lines BL1 and BL1 respectively receive from the adjacent bit lines are represented by the following equations, respectively; ##EQU5##
The bit line BL1 receives a noise .DELTA.V.sub.BL0 in the area a, a noise .DELTA.V.sub.BL2 in the area b, a noise .DELTA.V.sub.BL2 in the area c and a noise .DELTA.V.sub.BL0 in the area d. In addition, the bit line BL1 receives a noise .DELTA.V.sub.BL2 in the area a, a noise .DELTA.V.sub.BL0 in the area b, a noise .DELTA.V.sub.BL0 in the area c and a noise .DELTA.V.sub.BL2 in the area d. Thus, the noises .DELTA.V.sub.BL1' and .DELTA.V.sub.BL1' of capacitive coupling are the same.
(2) Noises .DELTA.V.sub.BL2' and .DELTA.V.sub.BL2' of capacitive coupling which the bit lines BL2 and BL2 respectively receive from the adjacent bit lines are represented by the following equations, respectively; ##EQU6##
The bit line BL2 receives a noise .DELTA.V.sub.BL1 in the area a, a noise .DELTA.V.sub.BL1 in the area b, a noise .DELTA.V.sub.BL3 in the area c and a noise .DELTA.V.sub.BL3 in the area d. The bit line BL2 receives a noise .DELTA.V.sub.BL3 in the area a, a noise .DELTA.V.sub.BL3 in the area b, a noise .DELTA.V.sub.BL1 in the area c and a noise .DELTA.V.sub.BL1 in the area d. Thus, the noises .DELTA.V.sub.BL2 ' and .DELTA.V.sub.BL2' of capacitive coupling are the same.
In the same manner, noises of capacitive coupling which paired bit lines respectively receive from the adjacent bit lines with respect to all of the bit line pairs are the same.
(3) Noises .DELTA.V.sub.BL0' and .DELTA.V.sub.BL0' of capacitive coupling with respect to the bit lines BL0 and BL0 in an end of a memory array are represented by the following equations, respectively; ##EQU7##
The bit line BL0 receives a noise .DELTA.V.sub.BL1 in the area c, and a noise .DELTA.V.sub.BL1 in the area d. The bit line BL0 receives a noise .DELTA.V.sub.BL1 in the area a and a noise .DELTA.V.sub.BL1 in the area b. Thus, the noises .DELTA.V.sub.BL0' and .DELTA.V.sub.BL0' of capacitive coupling are the same.
As described in the foregoing, in the semiconductor memory device shown in FIG. 3, noises of capacitive coupling which the paired bit lines respectively receive from adjacent bit lines at the time of reading out signals from the memory cells are the same. Therefore, the decrease in the read voltage difference caused by the noises of capacitive coupling can be completely prevented, so that a read margin can be increased and a soft error rate can be improved.
FIG. 4 is a diagram showing another example of the proposed semiconductor memory device. The semiconductor memory device shown in FIG. 4 is the same as the semiconductor memory device shown in FIG. 3 except that intersecting portions are further added at a point CP4 in ends of bit lines in bit line pairs BL0 and BL0, BL2 and BL2, . . . in odd numbers.
In the semiconductor memory devices, it is impossible to lay out each of the intersecting portions provided at the equally divided points CP1, CP2 and CP3 in a completely symmetrical shape with respect to the bit line pair. In the case of the semiconductor memory device shown in FIG. 3, there are two intersecting portions with respect to the bit line pairs BL1 and BL1, BL3 and BL3, . . . in even numbers, respectively, so that a balanced layout becomes possible as the entire bit line pair. For example, assuming that a bit line is an aluminum layer and an interconnection layer which can intersect with the bit line is a polysilicon (polycristaline silicon) layer, it is necessary that the bit lines BL1 and BL1 are formed of aluminum and polysilicon, respectively, in the intersecting portions at the equally divided point CP1 while being formed of polisilicon and aluminum, respectively, in the intersecting portions at the equally divided point CP3. Therefore, imbalance of parasitic capacitances of the bit line pair can be avoided. In the semiconductor memory device shown in FIG. 4, a dummy intersecting portions are added at the point CP4 such that capacitances are balanced with respect to the bit line pairs in odd numbers based on the similar effect. Therefore, a state in which capacitances are balanced with respect to all the bit lines can be achieved.
Although in the semiconductor memory devices shown in FIGS. 3 and 4, description is made on a case in which each of the bit line pairs is divided into four areas and the respective paired bit lines intersect with each other in suitable position or positions, the number of segments may be integral multiples of 4, to obtain the same effect. FIG. 5 shows an example of the 8 segments. In the example shown in FIG. 5, the shape shown in FIG. 3 is repeated two times. In the example shown in FIG. 5, it is obvious that the same effect as that shown in FIG. 3 is obtained.
However, the semiconductor memory devices shown in FIGS. 3 to 5 present the following problems. In the semiconductor memory devices shown in FIGS. 3 to 5, noises of capacitive coupling between different bit line pairs are cancelled while noises of capacitive coupling between the paired bit lines remain. For example, when signal charges are read out to the bit line BL0 so that a potential on the bit line BL0 changes, a potential on the bit line BL0 changes in the same direction as the potential on the bit line BL0. Consequently, the potential difference (signal potential difference) between the paired bit lines BL0 and BL0 becomes small. Such a noise component is almost the same as the noises of capacitive coupling between different bit line pairs, so that a margin for a reading operation is decreased.
Therefore, in the semiconductor memory devices shown in FIGS. 3 to 5, the noises of capacitive coupling between the different bit line pairs are cancelled while noise of capacitive coupling between the paired bit lines remain, so that read signal voltage characteristics are degraded, whereby a margin for a reading operation is decreased.
Japanese Patent Laying-Open Gazette No. 254489/1985 discloses that every other bit line out of a plurality of bit line pairs is twisted in the central portion thereof, so that array noises are eliminated. In addition, Japanese Patent Laying-Open Gazette No. 51096/1987 discloses that bit line pairs intersecting with each other at odd points and bit line pairs intersecting with each other at even points are alternately arranged, so that array noises are eliminated. Furthermore, THPM 16.5 "A 553K-Transister LISP Processor Chip", 1987 IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 202-203 discloses that bit line pairs in an SRAM cross each other in the center so that noises applied from other interconnections are cancelled.
However, any of the above described means fails to eliminate noises of capacitive coupling between the paired bit lines, as in the examples shown in FIGS. 3 to 5.